In a successive approximation routine, SAR, converter a comparator is used to determine the difference between a trial value and the analog value being converted. It is known in prior art successive approximation converters for the comparator to be formed from a number of voltage amplifier stages followed by a regenerative latch. The latch is a real component and hence suffers from both thermal noise and an input offset. The purpose of the amplifier stages is to reduce the effect of thermal noise and the offset by amplifying the voltage difference prior to it being provided to the latch. The amplifiers also have the effect of reducing “kickback” from the latch that can cause voltage spikes at the comparator inputs and which then have to be given time to settle out.
FIG. 1 is a circuit diagram of a voltage amplifier used in the prior art. The circuit comprises first and second field effect transistors Q1 and Q2 having their sources connected to a current source 10 which can also be conveniently be formed as a field effect transistor. A gate 12 of the first transistor Q1 acts as the non-inverting input to the amplifier, whereas a gate 14 of the second transistor Q2 acts as the inverting input. The drain terminal of transistor Q1 is connected to a second voltage supply rail labelled supply 2 via a resistor 16, and similarly the drain of the second transistor Q2 is connected to the second supply rail via a resistor 18. A connection to the drain of the first transistor Q1 also functions as the negative output, “on” of the amplifier, whereas a corresponding connection to the drain of the second transistor Q2 functions as the positive output, “op”. The transistors Q1 and Q2 are matched and hence can be regarded as having a first transconductance gm(1, 2) and consequently the gain of the amplifier is gm(1, 2) multiplied by the load resistance R.
The outputs “on” and “op” are connected to either a subsequent amplifier stage or to the comparator latch. The outputs therefore have to drive both the inherent capacitance of the following stage, such as the gate capacitance of a subsequent field effect transistor, and also have to drive the parasitic capacitances associated with the load and devices connected to the output nodes. The combination of the resistors 16 and 18 and the parasitic capacitance CP creates a pole, giving the circuit an overall low-pass frequency response.
It is also known to replace the load resistors 16 and 18 by active loads as shown in FIG. 2. In FIG. 2 a third transistor Q3, which is an NMOS device, has its drain connected to the drain of Q1 and its source connected to supply 2. The gate of the third transistor Q3 is connected to the drain of the third transistor Q3 such that the third transistor Q3 is in a diode connected configuration. A fourth transistor Q4 is similarly connected with respect to the second transistor Q2 so as to replace the second resistor 18. In addition a fifth transistor Q5 has its drain connected to the drain of the second transistor Q2 and its source connected to supply 2. However the gate of transistor Q5 is connected to the gate of transistor Q3. A sixth transistor Q6 is similarly connected, with its gate being connected to the gate of Q4 but its drain being connected to the drain of Q1. The transistors are matched such that transistors Q3 and Q4 have the same transconductance and transistors Q5 and Q6 have the same transconductance, but which may be different to that of transistors Q3 and Q4. In this arrangement the gain of the amplifier is gm(1, 2)÷(gm(3, 4)−gm(5, 6)). It is known to make the transconductance of the fifth and sixth transistors less than that of the third and fourth transistors to avoid the gain being too large.
It should be noted that making the gain larger has the effect of reducing the bandwidth of the amplifier (because the product of gain and bandwidth is generally a constant). In one respect this is desirable as it reduces a noise bandwidth of the circuit, however it also increases a settling time. As a result although the influence of noise would be reduced, the converter bit trials would have to run more slowly to allow the circuit to settle to full accuracy. As a result, amplifier stages have typically been made with gains of between 10 and 20.